1. Field of Invention
The present invention relates to a loop control circuit and a loop control method and more specifically, it relates to a loop control circuit that executes control of multiplexed loops with a minimum of overhead and a loop control method adopted therein.
2. Description of the Related Art
In processors such as DSPs (digital signal processors), loop instructions are used to execute a specific processing repeatedly.
The following is an explanation of a loop control method in the related art, given in reference to the drawings. FIG. 8 is a block circuit diagram that illustrates the operation of a loop control circuit in the related art. The number of stages in the stacks represents the number of multiplex loop levels in the hierarchy that can be achieved in this loop control apparatus. The circuit shown in FIG. 8 supports three loops. The term “stack” used in this context refers to an LIFO (last-in, first-out) memory. In the following explanation, recording data into a stack is referred to as “pushing down” and extracting data from the stack is referred to as “popping up”. In the loop control circuit in FIG. 8, the following three types of processing (phase S1) are concurrently executed in response to a loop instruction, as shown in the flowchart presented in FIG. 9.    The loop leading address corresponding to the next instruction following the loop instruction is pushed down into a “loop leading address” stack 4.    The value indicating the number of loop executions written in the loop instruction is pushed down into a “loop number” stack 5.    The loop trailing address written in the loop instruction is pushed down into a “loop trailing address” stack 6.
Then the loop control operation is executed as described below. “PC” in this context refers to a “program counter”. The PC is a memory that holds the value indicating the address of the next instruction.
First, in phase S2, the PC value and the stack value at the “loop trailing address” stack 6 are compared with each other (phase S2). If the PC value is equal to the stack value at the loop trailing address stack 6, the PC value is designated as the stack value at the loop leading address stack 4 (phase S3), and in phase S4, “1” is subtracted from the stack value at the loop number stack 5 (phase S4). If, on the other hand, it is decided in phase S2 that the PC value is not equal to the stack value at the loop trailing address stack 6, the loop control operation ends.
Next, in phase S5, the stack value at the loop number stack 5 is compared against “0” (phase S5). If the stack value at the loop number stack 5 is 0, the loop leading address stack 4, the loop number stack 5 and the loop trailing address stack 6 are popped up in phase S6 (phase S6). Then, the loop control operation ends.
If it is determined that the PC value is not equal to the stack value at the loop trailing address stack 6 in phase S2, “1” is added to the value at the phase program counter 1 (phase S7), before the loop control operation ends and the data processing shifts to execute the instruction at the next address.
Through this sequence of operations, the loop control apparatus executes the loop operation by using three types of information, i.e., the loop leading address, the value indicating the number of loop executions and the loop trailing address, set in the stacks in response to the loop instruction.
FIG. 10 presents an example of a loop instruction program. The instruction “loop instruction (1) 100, Loop 1” in FIG. 10 indicates that the execution of instruction 1˜5 is repeated 100 times. Likewise, the instruction “loop instruction (2) 2, Loop 2” indicates that the execution of instruction 3 and 4 is repeated twice. An instance of another loop instruction, i.e., the loop instruction (2) (an inner loop instruction) being present within the loop of the loop instruction (1) (an outer loop instruction) as shown in FIG. 10 is referred to as multiplexed loops. FIG. 11 shows the procedure through which instructions are processed when the program shown in FIG. 10 is executed. As shown in FIG. 11, by executing the program in FIG. 10, the instructions are processed in the order of; loop instruction (1)→instruction 1→instruction 2→loop instruction (2)→instruction 3→instruction 4→instruction 3→instruction 4→instruction 5→instruction 1→instruction 2→loop instruction (2)→ . . . →instruction 5. Through the program in FIG. 10, the processing of instruction 1 through 5 is repeatedly executed 100 times.
However, when executing multiplexed loop instructions in the loop control method in the related art, it is necessary to execute the inner loop instruction as many times as the number of times the outer loop instruction is executed. In FIG. 11, the loop instruction (2) 900 is repeatedly executed over 100 times. In reality, the loop instruction (2) simply instructs that the execution of instruction 3 and instruction 4 be repeated twice, and no actual data processing is executed. For this reason, there is a problem in that the presence of an inner loop instruction is bound to increase the overhead to lower the efficiency with which the overall program is processed.